An FPGA/FPAA-Based Rapid Prototyping Environment for Mixed Signal Systems

In this paper, we present a rapid prototyping environment for mixed signal systems. The environment consists of programmable mixed signal hardware together with a set of integrated CAD tools to enable fast prototyping of mixed signal designs from high-level speciications. The prototyping hardware comprises of eld-programmableanalog arrays and eld-programmable gate arrays on which the analog and digital sections of the design are respectively implemented. Field-programmable interconnect routes signals between multiple devices. A bank of data converters constitutes the interface between the analog and digital parts. Design tools are required to map the given design onto the prototyping hardware. The high-level design speciication is rst compiled into an intermediate format suitable for synthesis. Following this, the design is partitioned into analog and digital sections. The analog and digital subsystems are synthesized for the target FPAA and FPGA devices respectively. Connguration bitstreams are generated and downloaded on to the respective devices. Keywords: eld-programmable gate array (FPGA), eld-programmable analog array (FPAA), programmable interconnect , rapid prototyping, analog and mixed signal 1. MOTIVATION The VHDL-AMS Synthesis Environment (VASE) 1 being developed at the University of Cincinnati performs synthesis of mixed signal designs. From speciications in VHDL-AMS, the design is compiled and the netlist extracted into an intermediate format suitable for synthesis. After partitioning of the design into analog and digital sections, analog synthesis and digital synthesis of the respective subsystems is performed. Digital synthesis produces a structural view of the circuit, in particular of its data path, and a logic-level implementation of its control unit. 2 This involves solving two problems: xing the operations in space and time i.e. determining the time for their execution and their binding to resources, while satisfying system constraints. Scheduling, module selection, resource sharing and binding are the typical design steps. The rst step in analog synthesis is architecture generation. 3 It produces diierent possible system topologies for the given speciication. This is followed by component selection and constraint transformation. It involves selection of ASIC components from the library and propagation of system-level constraints to the component-level. For every system topology, transistor sizing is done to determine if the system performance constraints are satissed. We propose the use of a mixed signal prototyping system with VASE in order to evaluate the diierent system topologies. The advantage is that real-time validation of the hardware can be performed and the system can be tested in its target environment before hardware fabrication. …